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? e90603h0z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage av dd , dv dd 7v input voltage (all pins) v in v dd +0.5 to v ss ?.5 v output current (every each channel) i out 0 to 15 ma storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v reference input voltage v ref 2.0 v clock pulse width t pw1 , t pw0 11.2 ns (min.) to 1.1 s (max.) operating temperature topr ?0 to +85 ? description the CXD1178Q is an 8-bit high-speed d/a converter for video band use. it has an input/output equivalent to 3 channels of r, g and b. it is suitable for use of digital tv, graphic display, and others. features resolution 8-bit maximum conversion speed 40msps rgb 3-channel input/output differential linearity error 0.3lsb low power consumption 240 mw (200 ? load at 2 vp-p output) single 5 v power supply low glitch noise stand-by function structure silicon gate cmos ic 8-bit 40msps rgb 3-channel d/a converter 48 pin qfp (plastic) CXD1178Q
? CXD1178Q block diagram decoder decoder decoder decoder decoder decoder latches latches latches 32 35 34 42 29 41 40 31 30 33 28 39 38 46 45 44 43 27 37 36 48 47 2lsb s current cells 6msb s current cells clock generator 2lsb s current cells 6msb s current cells clock generator 2lsb s current cells 6msb s current cells clock generator current cells (for full scale) bias voltage generator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 (lsb) r0 (msb) r7 (lsb) g0 (msb) g7 (lsb) b0 b1 b2 b3 b4 b5 b6 (msb) b7 blk ce r1 r2 r3 r4 r5 r6 g1 g2 g3 g4 g5 g6 dv dd dv dd ro ro rck av dd av dd av dd av dd go go gck av ss dv ss dv ss bo bo bck vg vref iref vb
3 CXD1178Q pin configuration r0 r1 r2 r3 r4 r5 r6 r7 g0 g1 g2 g3 b7 b6 b5 b4 b3 b2 b1 b0 g7 g6 g5 g4 bck ro iref vref av ss vb dv ss dv ss gck rck ce blk ro go go bo bo vg av dd av dd av dd av dd dv dd dv dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pin description and i/o pins equivalent circuit pin no. symbol i/o equivalent circuit description 1 to 8 9 to 16 17 to 24 25 32 r0 to r7 g0 to g7 b0 to b7 blk vb i i o 1 24 dv dd dv ss to dv dd dv ss 25 dv dd dv ss 32 dv dd digital input r0 (lsb) to r7 (msb) g0 (lsb) to g7 (msb) b0 (lsb) to b7 (msb) blanking input. this is synchronized with the clock input signal for each channel. no signal at h (output 0 v). output condition at l . connect a capacitor of about 0.1 f.
4 CXD1178Q pin no. symbol i/o equivalent circuit description 27 28 29 30, 31 33 26 35 34 42 43 to 46 rck gck bck dv ss av ss ce iref vref vg av dd i i o i o dv dd dv ss 28 27 29 dv dd dv ss 26 av dd av ss 34 35 av dd av ss av dd av dd av ss 42 clock input. note) even though 1 channel and/ or 2 channel are used, be sure to input the clock signal to rck. digital gnd analog gnd chip enable input. this is not synchronized with the clock input signal. no signal (output 0 v) at h and minimizes power consumption. reference current output. connect a resistance 16 times 16r out that of output resistance value r out . reference voltage input. set full scale output value. connect a capacitor of about 0.1 f. analog v dd
5 CXD1178Q pin no. symbol i/o equivalent circuit description 37 39 41 36 38 40 47, 48 ro go bo ro go bo dv dd o av dd av ss 41 39 37 av dd av ss 36 38 40 current output pins. voltage output can be obtained by connecting a resistance. inverted current output. normally dropped to analog gnd. digital v dd
6 CXD1178Q (f clk =40 mhz, av dd =dv dd =5 v, r out =200 ? , v ref =2.0 v, ta=25 c) item resolution conversion speed integral non-linearity error differential non-linearity error output full-scale voltage output full-scale ratio ? 1 output full-scale current output offset voltage glitch energy crosstalk supply current analog input resistance input capacitance digital input voltage digital input current setup time hold time propagation delay time ce enable time ? 2 ce disable time ? 2 symbol n f clk e l e d v fs f sr i fs v os ge ct i dd i stb r in c i v ih v il i ih i il t s t h t pd t e t d measurement conditions av dd =dv dd =4.75 to 5.25 v ta= 40 to 85 c endpoint when 00000000 data input r out =75 ? when 1 mhz sine wave input 14.3mhz color bar ce= l data input ce= h vref av dd =dv dd =4.75 to 5.25 v ta= 20 to 75 c av dd =dv dd =4.75 to 5.25 v ta= 20 to 75 c r out =75 ? r out =75 ? ce= h l ce= l h min. 0.5 2.5 0.3 1.8 0 1 2.4 5 5 10 typ. 8 2.0 1.5 10 30 57 42 1 10 1.8 1.8 max. 40 2.5 0.3 2.2 3.0 15 1 48 2 9 0.8 5 4 4 unit bit msps lsb lsb v % ma mv pv s db ma m ? pf v a ns ns ns ms ms full-scale voltage of channel ? 1 full-scale output ratio = average of the full-scale voltage of the channels 1 100 (%) ? 2 when the external capacitor for the vg pin is 0.1 f.
7 CXD1178Q electrical characteristics measurement circuit analog input resistance measurement circuit digital input current CXD1178Q +5.25v av dd , dv dd av ss , dv ss v a maximum conversion velocity measurement circuit 8bit counter with latch 0.1 dv ss 25 26 32 27 28 29 clk 40mhz square wave oscilloscope 200 av ss 200 av ss 200 av ss av dd 0.1 3.3k av ss blk ce vb rck gck bck ro go bo vg vref iref 39 41 42 34 35 37 1k r0 to r7 1 to 8 g0 to g7 9 to 16 b0 to b7 17 to 24 }
8 CXD1178Q crosstalk measurement circuit digital waveform generator 200 av ss av dd 0.1 3.3k av ss blk ce vb rck gck bck ro go bo vg vref iref 0.1 dv ss 25 26 32 27 28 29 clk 40mhz square wave 1k 200 av ss 200 av ss 39 41 42 34 35 37 spectrum analizer all 1 r0 to r7 1 to 8 g0 to g7 9 to 16 b0 to b7 17 to 24 setup time hold time measurement circuit glitch energy 8bit counter with latch delay controller av dd 0.1 1.2k av ss 75 av ss 75 av ss 75 av ss 0.1 dv ss blk ce vb rck gck bck ro go bo vg vref iref 39 41 42 34 35 37 delay controller 25 26 32 27 28 29 1k oscilloscope clk 1mhz square wave r0 to r7 1 to 8 g0 to g7 9 to 16 b0 to b7 17 to 24 }
9 CXD1178Q dc characteristics measurement circuit 200 av ss 200 av ss 200 av ss av dd 0.1 3.3k av ss blk ce vb rck gck bck ro go bo vg vref iref 0.1 dv ss clk 40mhz square wave controller dvm 1k 25 26 32 27 28 29 39 41 42 34 35 37 r0 to r7 1 to 8 g0 to g7 9 to 16 b0 to b7 17 to 24 propagation delay time measurement circuit 200 av ss 200 av ss 200 av ss clk 10mhz square wave blk ce vb rck gck bck ro go bo vg vref iref 0.1 dv ss 25 26 32 27 28 29 frequency demultiplier av dd 0.1 3.3k av ss 1k 39 41 42 34 35 37 oscilloscope r0 to r7 1 to 8 g0 to g7 9 to 16 b0 to b7 17 to 24
10 CXD1178Q description of operation timing chart i/o chart (when full scale output voltage at 2.00 v) application circuit clk aa aa aa aaa aaa aaa aa aa aa aaa aaa aaa data d/a out t pw1 t pw0 2v t s t h t s t h t s t h t pd t pd t pd 100% 50% 0% dv dd av dd 0.1 2v (lsb) (msb) (lsb) 1 2 3 4 5 6 7 8 9 10 11 12 r (red) in g (green) in b (blue) in (msb) (lsb) (msb) 200 200 200 b (blue) out av ss g (green) out av ss r (red) out av ss 37 38 39 40 41 42 43 44 45 46 47 48 3.3k av ss av dd 1k av ss 0.1f dv ss dv ss clock in 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 input code msb lsb 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 output voltage 2.0 v 1.0 v 0 v application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . note) even though 1 channel and/ or 2 channel are used, be sure to input the clock signal to rck(pin 27).
11 CXD1178Q notes on operation how to select the output resistance the CXD1178Q is a d/a converter of the current output type. to obtain the output voltage connect the resistance to current output pins (ro, go and bo). for specifications we have; output full scale voltage v fs =1.8 to 2.2 [v] output full scale current i fs =less than 15 [ma] calculate the output resistance value from the relation of v fs =i fs r out . also, 16 times resistance of the output resistance is connected to reference current pin iref. in some cases, however, this turns out to be a value that does not actually exist. in such a case a value close to it can be used as a substitute. here please note that v fs becomes v fs =v ref 16r out /r ir . v ref is the voltage set at the vref pin and r out is the resistance connected to current output pins (ro, go and bo) while r ir is connected to iref. increasing the resistance value can curb power consumption. on the other hand glitch energy and data settling time will inversely increase. set the most suitable value according to the desired application. phase relation between data and clock to obtain the expected performance as a d/a converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. be sure to satisfy the provisions of the setup time (t s ) and hold time (t h ) as stipulated in the electrical characteristics. power supply and ground to reduce noise effects separate analog and digital systems in the device periphery. for power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 f, as close as possible to the pin. latch up analog and digital power supply have to be common at the pcb power supply source. this is to prevent latch up due to voltage difference between av dd and dv dd pins when power supply is turned on. on inverted current output pins the ro, go and bo are the inverted current output terminal as described in the pin description. the sums shown below become the constant value for any input data. a) the sum of the currents output from the ro and ro pins. b) the sum of the currents output from the go and go pins. c) the sum of the currents output from the bo and bo pins. however, the output current from the ro, go and bo pins is not guaranteed of its performances such as linearity errors, etc. on output full-scale voltage when the output full-scale voltage is used without adjustment in the application that uses the rgb signal, the color balance may be broke. clock input signal even though 1 channel and/ or 2 channel are used, be sure to input the clock signal to rck(pin 27).
12 CXD1178Q latch up prevention the CXD1178Q is a cmos ic which required latch up precautions. latch up is mainly generated by the lag in the voltage rising time of av dd (pins 43 to 46) and dv dd (pins 47 and 48), when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources b. when analog and digital supplies are from a common source (i) (ii) 43 CXD1178Q av ss av dd 44 45 46 33 av dd dv dd dv ss av ss cc 31 dv ss +5v +5v 30 47 48 digital ic dv dd 43 CXD1178Q av ss 44 45 46 33 av dd dv dd dv ss av ss cc 31 dv ss +5v 30 47 48 digital ic dv dd 43 CXD1178Q av ss 44 45 46 33 av dd dv dd dv ss av ss cc 31 dv ss +5v 30 47 48 digital ic dv dd
13 CXD1178Q 2. example when latch up easily occurs a. when analog and digital supplies are from different sources b. when analog and digital supplies are from common source (i) (ii) 43 CXD1178Q av ss av dd 44 45 46 33 av dd dv dd dv ss av ss cc 31 dv ss +5v +5v 30 47 48 digital ic dv dd 43 CXD1178Q av ss 44 45 46 33 av dd dv dd dv ss av ss cc 31 dv ss +5v 30 47 48 digital ic dv dd av dd 43 CXD1178Q av ss 44 45 46 33 av dd dv dd dv ss av ss c 31 dv ss +5v 30 47 48 digital ic dv dd av dd
14 CXD1178Q example of representative characteristics output full scale voltage vs. reference voltage reference voltage v ref [v] output full scale voltage v fs [v] 100 glitch energy vs. output resistance output resistance r out [ ? ] 200 crosstalk ct [db] crosstalk vs. output frequency output frequency f out [hz] 2.0 1.0 0 1.0 2.0 200 100 av dd =dv dd =5v v ref =2.0v r ir 16r out ta=25 c 60 50 40 100k 1m 10m av dd =dv dd =5v v ref =2.0v r out =200 ? r ir =3.3k ? ta=25 c av dd =dv dd =5v r out =200 ? r ir =3.3k ? ta=25 c 2.0 1.9 0 25 0 25 50 75 av dd =dv dd =5v v ref =2.0v r out =200 r ir =3.3k ? ? 40 85 output full scale v fs [v] output full scale voltage vs. ambient temperature ambient temperature ta [ c] glitch energy ge [pv s]
sony code eiaj code jedec code m package structure package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.24 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 ?0.05 + 0.1 qfp-48p-l04 qfp048-p-1212 0.7g 0.15 package outline unit : mm CXD1178Q 15
16 CXD1178Q sony corporation sony code eiaj code jedec code m package structure package material lead treatment lead material package mass epoxy resin palladium plating copper alloy 48pin qfp (plastic) 15.3 0.4 12.0 0.1 + 0.4 0.8 0.3 0.1 + 0.15 0.24 13 24 25 36 37 48 112 2.2 0.15 + 0.35 0.9 0.2 0.1 0.1 + 0.2 13.5 0.15 0.05 + 0.1 qfp-48p-l04 qfp048-p-1212 0.7g 0.15 package outline unit : mm

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